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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. a 01/18/08 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. is62wv20488all is62wv20488bll 2m x 8 high-speed low power cmos static ram january 2008 features ? high-speed access times: 25, 35 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single power supply ? v dd 1.65v to 2.2v (is62wv20488all) speed = 35ns for vcc = 1.65v to 2.2v ? v dd 2.4v to 3.6v (is62wv20488bll) speed = 25ns for vcc = 2.4v to 3.6v ? packages available: ? 48-ball minibga (9mm x 11mm ) ? 44-pin tsop (type ii) ? industrial temperature support ? lead-free available description the issi is62wv20488all/bll is a high-speed, low power, 2m-word by 8-bit cmos static ram. the is62wv20488all/bll is fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design tech- niques, yields higher performance and low power con- sumption devices. when cs1 is high (deselected) or when cs2 is low (deselected) or when cs1 is low, cs2 is high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. the is62wv20488all/bll operates from a single power supply and all inputs are ttl-compatible. the is62wv20488all/bll is available in 48 ball mini bga and 44-pin tsop (type ii) packages. functional block diagram a0-a20 cs1 cs2 oe we 2m x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 01/18/08 is62wv20488all is62wv20488bll pin descriptions a0-a20 address inputs cs1 , cs2 chip enable input oe output enable input we write enable input i/o0-i/o7 data input / output v dd power gnd ground nc no connection 48-pin mini bga (m ) (9mm x 11mm) 44-pin tsop (type ii ) 1 2 3 4 5 6 a b c d e f g h nc nc nc gnd v dd nc nc a18 oe nc nc nc nc nc a19 a8 a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 cs1 i/o1 i/o3 i/o4 i/o5 we a11 cs2 i/o0 i/o2 v dd gnd i/o6 i/o7 a20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a0 a1 a2 a3 a4 cs1 i/o0 i/o1 vdd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc nc nc a20 a18 a17 a16 a15 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a14 a13 a12 a11 a10 a19 nc nc 44 43 42 41 pin configuration
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. a 01/18/08 is62wv20488all is62wv20488bll absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v v dd v dd relates to gnd ?0.3 to 4.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode we we we we we cs1 cs1 cs1 cs1 cs1 cs2 oe oe oe oe oe i/o operation v dd current not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x output disabled h l h h high-z i cc read h l h l d out i cc write l l h x d in i cc capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 01/18/08 is62wv20488all is62wv20488bll operating range (v dd ) (is62wv20488bll) (1) range ambient temperature v dd (25 n s ) commercial 0c to +70c 2.4v-3.6v industrial ?40c to +85c 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 25ns. when operated in the range of 3.3v + 5%, the device meets 15ns. operating range (v dd ) (is62wv20488all) range ambient temperature v dd (35 n s ) commercial 0c to +70c 1. 65v-2.2v industrial ?40c to +85c 1. 65v-2.2v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. a 01/18/08 is62wv20488all is62wv20488bll dc electrical characteristics (over operating range) v dd = 2.4v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 1.8 ? v v ol output low voltage v dd = min., i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 1.65v-2.2v symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 01/18/08 is62wv20488all is62wv20488bll power supply characteristics (1) (over operating range) -25 -35 symbol parameter test conditions min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. ? 25 ? 20 ma supply current i out = 0 ma, f = f max ind. ? 30 ? 25 typ. (2) 20 17 i cc 1 operating v dd = max., com. ? 10 ? 10 ma supply current i out = 0 ma, f = 0 ind. ? 15 ? 15 i sb 1 ttl standby current v dd = max., com. ? 5 ? 5 ma (ttl inputs) v in = v ih or v il ind. ? 6 ? 6 cs1 v ih , f = 0, cs2 = v il i sb 2 cmos standby v dd = max., com. ? 1.5 ? 1.5 ma current (cmos inputs) cs1 v dd ? 0.2v, ind. ? 1.5 ? 1.5 cs2 0.2v, typ. (2) 0.8 0.5 v in v dd ? 0.2v, or v in 0.2v , f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. a 01/18/08 is62wv20488all is62wv20488bll ac test loads figure 1 figure 2 3070 5 pf including jig and scope 3150 output 1.8v/3.3v 3070 30 pf including jig and scope 3150 output 1.8v/3.3v ac test conditions (low power) parameter unit unit (2.4v-3.6v) (1.65v-2.2v) input pulse level 0.4v to v dd -0.3v 0.4v to v dd -0.2v input rise and fall times 1.5ns 1.5ns input and output timing v dd /2 v dd /2 and reference level (v ref ) output load see figures 1 and 2 see figures 1 and 2
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 01/18/08 is62wv20488all is62wv20488bll read cycle switching characteristics (1) (over operating range) 25ns 35ns symbol parameter min. max. min. max. unit t rc read cycle time 25 ? 35 ? ns t aa address access time ? 25 ? 35 ns t oha output hold time 4 ? 4 ? ns t acs1/ t acs2 cs1 /cs2 access time ? 25 ? 35 ns t doe oe access time ? 12 ? 15 ns t hzoe (2) oe to high-z output ? 8 ? 10 ns t lzoe (2) oe to low-z output 5 ? 5 ? ns t hzcs1/ t hzcs2 (2) cs1 /cs2 to high-z output 0 8 0 10 ns t lzcs1/ t lzcs2 (2) cs1 /cs2 to low-z output 10 ? 10 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0 .4 to v dd -0.2v/0.4v to v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs1 = oe = v il , cs2 = we = v ih ) data valid previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. a 01/18/08 is62wv20488all is62wv20488bll ac waveforms read cycle no. 2 (1,3) ( cs1 , cs2, oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , cs1 = v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low and cs2 high transition. t rc t oha t aa t doe t lzoe t acs1/ t acs2 t lzcs1/ t lzcs2 t hzoe high-z data valid t hzcs address oe cs1 cs2 dout
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 01/18/08 is62wv20488all is62wv20488bll write cycle switching characteristics (1,2) (over operating range) 25 ns 35 ns symbol parameter min. max. min. max. unit t wc write cycle time 25 ? 35 ? ns t scs1/ t scs2 cs1/ cs2 to write end 18 ? 25 ? ns t aw address setup time to write end 15 ? 25 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe (4) we pulse width 18 ? 30 ? ns t sd data setup to write end 12 ? 15 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 12 ? 20 ns t lzwe (3) we high to low-z output 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0.4 to v dd -0.2v/0.4v to v dd -0.3v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of cs1 low, cs2 high and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 4. t pwe > t hzwe + t sd when oe is low. ac waveforms write cycle no. 1 ( cs1 /cs2 controlled, oe = high or low ) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. a 01/18/08 is62wv20488all is62wv20488bll ac waveforms write cycle no. 2 ( we controlled: oe is high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 01/18/08 is62wv20488all is62wv20488bll data retention switching characteristics symbol parameter test condition min. typ. (1) max. unit v dr vcc for data retention see data retention waveform 1.2 3.6 v i dr data retention current vcc = 1.2v, cs1/ cs2 vcc ? 0.2v ? 0.5 1.5 ma t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns note: 1. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. data retention waveform ( cs1 cs1 cs1 cs1 cs1 controlled) data retention waveform (cs2 controlled) v cc cs1 v cc - 0.2v t sdr t rdr v dr cs1 gnd 3.0v 2.2v data retention mode v cc cs2 0.2v t sdr t rdr v dr 0.4v cs2 gnd 3.0 2.2v data retention mode
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. a 01/18/08 is62wv20488all is62wv20488bll ordering information industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 25 is62wv20488bll-25mi 48 m ini bga (9mm x 11mm) IS62WV20488BLL-25MLI 48 mini bga (9mm x 11mm), lead-free is62wv20488bll-25ti tsop (type ii) is62wv20488bll-25tli tsop (type ii), lead-free industrial range: -40c to +85c voltage range: 1.65v to 2.2v speed (ns) order part no. package 35 is62wv20488all-35mi 48 m ini bga (9mm x 11mm) is62wv20488all-35mli 48 mini bga (9mm x 11mm), lead-free is62wv20488all-35ti tsop (type ii) is62wv20488all-35tli tsop (type ii), lead-free
packaging information integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: m (48-pin) notes: 1. controlling dimensions are in millimeters. seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 mbga - 7.2mm x 8.7mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0 .24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 8.60 8.70 8.80 0.339 0.343 0.346 d1 5.25bsc 0.207bsc e 7.10 7.20 7.30 0.280 0.283 0.287 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 9mm x 11mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0.24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 10.90 11.00 11.10 0.429 0.433 0.437 d1 5.25bsc 0.207bsc e 8.90 9.00 9.10 0.350 0.354 0.358 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 .? ? 0.047 a1 0.25 ? 0.40 0.010 ? 0.016 a2 0.60 ? ? 0.024 ? ? d 7.90 8.00 8.10 0.311 0.314 0.319 d1 5.60bsc 0.220bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 4.00bsc 0.157bsc e 0.80bsc 0.031bsc b 0.40 0.45 0.50 0.016 0.018 0.020 mini ball grid array package code: m (48-pin)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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